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L6701
3 Phase Controller for VR10, VR9 and K8 CPUs
Features
MULTI-DAC: VR9, VR10 AND K8 DAC SELECTABLE THROUGH SINGLE PIN 0.7% OUTPUT VOLTAGE ACCURACY ADJUSTABLE REFERENCE OFFSET HIGH CURRENT INTEGRATED DRIVERS DYNAMIC VID MANAGEMENT ACCURATE FULLY-DIFFERENTIAL LOADLINE CURRENT-SENSE ACROSS MAIN INDUCTORS MAKES BOM INDEPENDENT ON THE LAYOUT PRECISE CURRENT-SHARING AND OCP ACROSS LS MOSFETS CONSTANT OVER-CURRENT PROTECTION FEEDBACK DISCONNECTION PROTECTION PRELIMINARY OV PROTECTION OSCILLATOR INTERNALLY FIXED AT 100kHz (300kHz RIPPLE) EXT ADJUSTABLE SS_END / PGOOD SIGNAL INTEGRATED REMOTE-SENSE BUFFER PWSSO36 PACKAGE WITH EXPOSED PAD PowerSSO-36

Description
L6701 is an extremely simple, low-cost solution to implement a three phase step-down controller with integrated high-current drivers in a compact PowerSSO-36 package with exposed pad. The device embeds three selectable DACs: with a single pin it is possible to program the device to work in compatibility with VR9, VR10 or K8 applications managing D-VID with 0.7% output voltage accuracy over line and temperature variations. Additional programmable offset can be added to the reference voltage with a single external resistor. Fast protection against load over current let the system works in Constant Current mode until UVP. Preliminary OVP allows full load protection in case of startup with failed HS. Furthermore, feedback disconnection prevents from damaging the load in case of misconnections in the system board. Combined use of DCR and RDS(on) current sensing assures precision in voltage positioning and safe current sharing and OCP per each phase.

Applications
HIGH CURRENT VRM / VRD FOR DESKTOP / SERVER/ WORKSTATION CPUs HIGH DENSITY DC / DC CONVERTERS
Order codes
Part number L6701 L6701TR Package PowerSSO-36 PowerSSO-36 Packing Tube Tape & Reel Rev 1 1/44
www.st.com 44
December 2005
L6701
Contents
1 2 Device Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . . 11
5.1 5.2 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 7
VID Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Configuring the Device: DAC Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.1 Single-Wire CPU Automatic Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8
Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.1 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9
Current Sharing Loop and Current Reading . . . . . . . . . . . . . . . . . . . . . . . 20
9.1 9.2 Current Sharing Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Current Reading for Current Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10
Output Voltage Positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10.1 10.2 10.3 10.4 10.5 Load-Line (Droop Function - Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Fully-Differential Load-Line (Droop Function - Optional) . . . . . . . . . . . . . . . 22 Offset (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Remote Voltage Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Maximum Duty Cycle limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/44
L6701
11 12
Dynamic VID Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Soft Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12.1 Low-Side-Less Startup (LSLess) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
13
Output voltage Monitor and Protections . . . . . . . . . . . . . . . . . . . . . . . . . . 29
13.1 13.2 13.3 13.4 13.5 13.6 Under Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Preliminary Over Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Over Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Feedback Disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PGOOD (Only for VR9 and K8 Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Over Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
14 15
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 System Control Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
15.1 Compensation Network Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
16
Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
16.1 16.2 16.3 Power Components and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Small Signal Components and Connections . . . . . . . . . . . . . . . . . . . . . . . . . 39 Embedding L6701-based VRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
17 18
Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3/44
1 Device Description
L6701
1
Device Description
L6701 is multi-phase PWM controller with embedded high-current drivers that provides complete control logic and protections for a high-performance step-down DC-DC voltage regulator, optimized for advanced microprocessor power supply. Multi-phase buck is the simplest and most cost-effective topology employable to satisfy the increasing current demand of newer microprocessors and the modern high-current DC/DC converters and POLs requirements. It allows distributing equally load and power between the phases using smaller, cheaper and most common external power MOSFETs and inductors. Moreover, thanks to the equal phase-shift between each phase, the input and output capacitor count results in being reduced. Phase-interleaving causes in fact input rms current and output ripple voltage reduction and shows an effective output switching frequency increase: the 100kHz free-running frequency per phase, externally adjustable through a resistor, results multiplied on the output by the number of phases so reaching 300kHz in free-running. L6701 includes multiple DACs, selectable through an apposite pin, allowing compatibility with both Intel VR9, VR10 and AMD Hammer specifications, also performing D-VID transitions accordingly. In particular for Intel CPUs, it allows to automatically recognize the CPU with a single-wire connection, without any additional external component, by proper connecting the selector pin to the proper CPU pin. Precise voltage positioning (LL) is possible thanks to an accurate fully-differential current-sense across the main inductors still using only two pins for current-reading (pat. pend.): this makes any BOM insensitive to the board layout saving time in the design stage. The device internally balance the current driven by each phase by sensing the voltage drop across the LS MOSFET RDS(on). OC protection is effective with a threshold for each phase causing the device to work in constant-current mode. The controller provides output voltage protections to avoid any load damage due to failed components and/or feedback misconnections. Over-Voltage protects the load from dangerous over stress latching immediately the device by turning-on the lower driver and driving high the FAULT pin. Furthermore, preliminary-OVP protection also allows the device to protect the load from dangerous OVP when VCC is not above the UVLO threshold. Under-Voltage protection causes the device to stop switching when set while Over-Current protection, with a threshold for each phase, causes the device to enter in constant current mode until the latched UVP. L6701 implements soft-start increasing the reference up to the final value in 2048 clock cycles in closed loop regulation. Low-Side-Less feature allows the device to perform soft-start over pre-biased output avoiding dangerous current return through the main inductors as well as negative spike at the load side. The compact PowerSSO-36 package with exposed thermal pad allows dissipating the power to drive the external MOSFET through the system board.
4/44
L6701
2 Pins description and connection diagrams
2
Figure 1.
Pins description and connection diagrams
Pins connection (Top view)
SGND VCC LGATE1 PGND LGATE2 LGATE3 BOOT1 UGATE1 PHASE1 BOOT2 UGATE2 PHASE2 BOOT3 UGATE3 PHASE3 SSEND / PGOOD DAC_SEL OSC / EN / FAULT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
COMP FB VSEN CSCS+ ISEN1 ISEN2 ISEN3 FBG FBR VID5 VID0 VID1 VID2 VID3 VID4 REF_OUT REF_IN
2.1
Table 1.
Pin description
Pins description
Name SGND VCC LGATE1 PGND LGATE2 LGATE3 Function All the internal references are referred to this pin. Connect to the PCB Signal Ground. Device Power Supply and LS driver supply. Operative voltage is 12V 15%. Filter with at least 1F MLCC vs. ground. Channel 1 LS Driver Output. A small series resistor helps in reducing device-dissipated power. LS Drivers return path. Connect to Power ground Plane. Channel 2 LS Driver Output. A small series resistor helps in reducing device-dissipated power. Channel 3 LS Driver Output. A small series resistor helps in reducing device-dissipated power. Channel 1 HS driver supply. Connect through a capacitor (100nF typ.) to PHASE1 and provide necessary Bootstrap diode. A small series resistor upstream the boot diode helps in reducing Boot capacitor overcharge. Channel 1 HS driver output. A small series resistors helps in reducing device-dissipated power. Channel 1 HS driver return path. It must be connected to the HS1 MOSFET source and provides return path for the HS driver of channel 1. Pin n 1 2 3 4 5 6
7
BOOT1
8
UGATE1
9
PHASE1
5/44
2 Pins description and connection diagrams
L6701
Table 1.
Pin n
Pins description (continued)
Name Function Channel 2 HS driver supply. Connect through a capacitor (100nF typ.) to PHASE2 and provide necessary Bootstrap diode. A small series resistor upstream the boot diode helps in reducing Boot capacitor overcharge. Channel 2 HS driver output. A small series resistors helps in reducing device-dissipated power. Channel 2 HS driver return path. It must be connected to the HS2 MOSFET source and provides return path for the HS driver of channel 2. Channel 3 HS driver supply. Connect through a capacitor (100nF typ.) to PHASE3 and provide necessary Bootstrap diode. A small series resistor upstream the boot diode helps in reducing Boot capacitor overcharge. Channel 3 HS driver output. A small series resistors helps in reducing device-dissipated power. Channel 3 HS driver return path. It must be connected to the HS3 MOSFET source and provides return path for the HS driver of channel 3. SSEND - Intel VR10 Mode. Soft Start END Signal. Open Drain Output set free after SS has finished and pulled low when triggering any protection. Pull up to 5V (typ) or lower, if not used it can be left floating. PGOOD - Intel VR9 & AMD Hammer Mode. Open Drain Output set free after SS has finished and pulled low when VSEN is lower than the relative threshold. Pull up to 5V (typ) or lower, if not used it can be left floating. DAC SELection pin. It allows programming the DAC table for the regulation. Internally pulled-up to 5V. Short to GND to program VR9 DAC, leave floating to program K8 DAC while connect to GND through 82k to program VR10 DAC. Information about the selected DAC is latched before the system start-up. See Section 7.1 for connections to enable CPU auto-detection. OSC: It allows programming the switching frequency FSW of each channel. Switching frequency can be increased according to the resistor connected from the pin vs. SGND with a gain of 4kHz/A (see Section 14). Leaving the pin floating it programs a switching frequency of 100kHz per phase (300kHz on the load). EN: Forced low, the device stops operations with all MOSFETs OFF: all the protections are disabled except for Preliminary Over Voltage. When set low it resets the device from any latching condition. FAULT: The pin is forced high (5V) to signal an OVP / UVP FAULT: to recover from this condition, cycle VCC or the OSC pin. See Section 13 for details.
10
BOOT2
11
UGATE2
12
PHASE2
13
BOOT3
14
UGATE3
15
PHASE3
16
SSEND / PGOOD
17
DAC_SEL
18
OSC / EN / FAULT
6/44
L6701
Table 1.
Pin n
2 Pins description and connection diagrams
Pins description (continued)
Name Function Reference Input for the regulation. Connect directly or through a resistor to the REF_OUT pin. See Section 10.3 for details. This pin is used as input for the protections. Reference Output. Connect directly or through a resistor to the REF_IN pin. See Section 10.3 for details. Voltage IDentification Pins. Internally pulled up by 12.5A to 5V, connect to SGND to program a '0' or leave floating to program a '1'. They allow programming output voltage as specified in Table 5, Table 6 and Table 7 according to DAC_SEL status. Remote Buffer Non Inverting Input. Connect to the positive side of the load to perform remote sense. See Section 16 for proper layout of this connection. Remote Buffer Inverting Input. Connect to the negative side of the load to perform remote sense. See Section 16 for proper layout of this connection. LS Current Sense Pins. These pins are used for current balance phase-to-phase as well as for the system OCP. Connect through a resistor RISEN to the relative PHASEx pin. See Section 9 and Section 13.6 for details. Droop Current Sense non-inverting input. Connect through RPH-CPH network to the main inductors. Directly connect to output voltage when Droop function is not required. See Section 10.1 and Section 10.2 for details. Droop Current Sense inverting input. Connect through resistor RD to the main inductors common node. Leave floating when Droop Function is not required. See Section 10.1 and Section 10.2 for details. This pin also monitors the output for any feedback disconnection. See Section 13.4 for details. Remote Buffer Output. It manages OVP and UVP protections and PGOOD (when applicable). See Section 13 for details. Error Amplifier Inverting Input. Connect with a resistor RFB vs. VSEN and with an RF - C F toward COMP. Error Amplifier Output. Connect with an RF - CF vs. FB. The device cannot be disabled by pulling down this pin. Thermal pad connects the Silicon substrate and makes good thermal contact with the PCB to dissipate the power necessary to drive the external MOSFETs. Connect to the PGND plane with several VIAs to improve thermal conductivity.
19
REF_IN
20
REF_OUT
21 to 26
VID4 to VID0, VID5
27
FBR
28
FBG
29 to 31
ISEN3 to ISEN1
32
CS+
33
CS-
34 35
VSEN FB
36
COMP
PAD
THERMAL PAD
7/44
3 Maximum Ratings
L6701
3
3.1
Table 2.
Symbol VCC
Maximum Ratings
Absolute maximum ratings
Absolute Maximum Ratings
Parameter to PGND Boot Voltage Value 15 15 15 LGATEx, PHASEx, to PGNDx VID0 to VID5 All other Pins to PGNDx -0.3 to VCC + 0.3 -0.3 to 5 -0.3 to 7 26 TBD Unit V V V V V V V V
VBOOTx - VPHASEx VUGATEx - V PHASEx
VPHASEx
Positive Peak Voltage; T<20ns @ 600kHz Negative Peak Voltage;
3.2
Table 3.
Thermal data
Thermal data
Parameter Thermal Resistance Junction to Ambient (Device soldered on 2s2p PC Board) Thermal Resistance Junction to Case Maximum Junction Temperature Storage Temperature Range Junction Temperature Range Maximum Power Dissipation at 25C (Device soldered on 2s2p PC Board) Value 30 1 150 -40 to 150 0 to 125 3.3 Unit C/W C/W C C C W
Symbol RTHJA RTHJC TMAX TSTG TJ PTOT
8/44
L6701
4 Electrical specifications
4
4.1
Table 4.
Symbol
Electrical specifications
Electrical characteristics
Electrical Characteristics (VCC = 12V15%, TJ = 0C to 70C unless otherwise specified).
Parameter Test conditions Min. Typ. Max. Unit
Supply Current and Power-ON ICC IBOOTx VCC Supply current BOOTx Supply Current VCC Turn-ON VCC Turn-OFF Pre-OVP Turn-ON UVLOOVP Pre-OVP Turn-OFF Oscillator and Inhibit FSW OSCIL dMAX VOSC FAULT Main Oscillator Accuracy Disable Thresholds OSC = OPEN; IISENx = 0A Maximum Duty Cycle OSC = OPEN; IISENx = 35A PWMx Ramp Amplitude Voltage at Pin OSC OVP Active 40 3 5 % V V OSC = OPEN OSC = OPEN; TJ = 0C to 125C 90 0.5 80 100 110 kHz V % HGATEx and LGATEx = OPEN BOOTx = 12V HGATEx = OPEN; PHASEx to PGNDx; BOOTx = 12V VCC Rising VCC Falling VCC Rising VCC Falling 3 7 3.8 17 0.7 9.2 mA mA V V V V
UVLOVCC
Reference and DAC FBR = V OUT; FBG = GNDOUT; kVID VR10 and VR9 DACs; VOUT > 1V Output Voltage Accuracy FBR = V OUT; FBG = GNDOUT; K8 DAC; V OUT > 1V IVID VID IL VID Input Thresholds VID IH VR9 and VR10 Mode; Input Low K8 Mode; Input Low 0.8 2 V V VID Pull-up Current VR9 and VR10 Mode; Input Low K8 Mode; Input Low -1 25 0.4 0.8 1 % A V V -0.7 0.7 %
9/44
4 Electrical specifications
L6701
Table 4.
Symbol
Electrical Characteristics (continued) (VCC = 12V15%, TJ = 0C to 70C unless otherwise specified).
Parameter Test conditions Min. Typ. Max. Unit
Error Amplifier and Remote Buffer A0 SR EA DC Gain Slew Rate RB DC Gain CMRR Remote Buffer Common Mode Rejection Ratio COMP = 10pF to SGND 80 15 1 40 dB V/s V/V dB
Differential Current Sensing and Offset IOCTH kIDROOP IOFFSET Over Current Threshold Droop Current Deviation Offset Current IDROOP = 0 to 105A; RD=5.1k -3 10 11.5 35 3 13 A A A
Gate Drivers tRISE_UGA
TEx
HS Rise Time HS Source Current HS Sink Resistance LS Rise Time LS Source Current LS Sink Resistance
BOOTx - PHASEx = 10V; CUGATEx to PHASEx = 3.3nF BOOTx - PHASEx = 10V BOOTx - PHASEx = 12V VCC = 10V; CLGATEx to PGNDx = 5.6nF VCC = 10V VCC = 12V
15 1.5 2.5 20 1.5 1.8
ns A ns A
IUGATEx RUGATEx tRISE_LGA TEx ILGATEx RLGATEx
Protections OVP Over Voltage Protection VSEN Rising, VR10 and K8 Mode VSEN Rising, VR9 Mode FBR Rising, VR10 and K8 Mode FBR Rising, VR9 Mode Hysteresis UVP PGOOD VSSEND/
PGOOD
1.85 2.05 1.8 2.0
1.9 2.1 1.9 2.1 300
1.95 2.15 2.0 2.2
V V V V mV
Pre-OVP
Preliminary Over voltage Protection Under Voltage Protection PGOOD Threshold SSEND / PGOOD Voltage Low
VSEN Falling; Below VID K8 and VR9 Mode; VSEN Falling; Below VID I = -4mA
-475 -280
-400 -230
-325 -180 0.4
mV mV V
10/44
L6701
5 Typical application circuit and block diagram
5
5.1
Figure 2.
VIN
Typical application circuit and block diagram
Application circuit
Typical application circuit
LIN to BOOT1 CIN VCC BOOT1 7 VIN to BOOT2 to BOOT3
GNDIN
2
4 1
PGND SGND
UGATE1
8
HS1 L1
PHASE1
9
17
DAC_SEL
LGATE1
3
LS1 RISEN
18
OSC/EN/FAULT
ISEN1
31
26 21 22 23 24 25
VID5 VID4 VID3 VID2 VID1 VID0
BOOT2
10
VIN
UGATE2
11
HS2 L2 Vcc_core
PHASE2
12
LGATE2
5
LS2 RISEN
COUT
LOAD
19
REF_IN
ISEN2
30
L6701
COS
ROS 20 36
BOOT3
13
VIN
REF_OUT COMP
UGATE3
14
HS3 L3
CF RF 35
PHASE3
15
RPH
RPH
FB ISEN3
29
RISEN CPH
RFB 34 CS+ VSEN CS-
32 33 RD
27 28
FBR FBG SSEND / PGOOD 16 PGOOD
L6701 REFERENCE SCHEMATIC
RPH
LGATE3
6
LS3
11/44
5 Typical application circuit and block diagram
L6701
Figure 3.
VIN
Typical Application Circuit: Fully Differential Current Sense (Pat.Pend.)
LIN to BOOT1 CIN VCC BOOT1 7 VIN to BOOT2 to BOOT3
GNDIN
2
4 1
PGND SGND
UGATE1
8
HS1 L1
PHASE1
9
17
DAC_SEL
LGATE1
3
LS1 RISEN
18
OSC/EN/FAULT
ISEN1
31
26 21 22 23 24 25
VID5 VID4 VID3 VID2 VID1 VID0
BOOT2
10
VIN
UGATE2
11
HS2 L2 Vcc_core
PHASE2
12
LGATE2
5
LS2 RISEN
COUT
LOAD
19
REF_IN
ISEN2
30
L6701
COS
ROS 20 36
BOOT3
13
VIN
REF_OUT COMP
UGATE3
14
HS3 L3
CF RF 35
PHASE3
15
RPH
RPH
FB ISEN3
29
RISEN CPH CPH CPH
RFB 34 CS+ VSEN CSFBR FBG
32
33
RD RD RD
27 28
SSEND / PGOOD
16
RPH
LGATE3
6
LS3
PGOOD
L6701 FULLY DIFFERENTIAL REFERENCE SCHEMATIC
12/44
L6701
5 Typical application circuit and block diagram
5.2
Figure 4.
Block diagram
Block diagram
PHASE1 PHASE2 PHASE3 UGATE1 UGATE2 UGATE3 LGATE1 LGATE2 LGATE3
VCC PGND LS3 LOGIC PWM ADAPTIVE ANTI CROSS CONDUCTION
CURRENT SHARING CORRECTION
BOOT1
BOOT2
VCC
VCC
PGND
VCC
PGND
VCC
PGND
PGND
SGND
HS1
LS1 LOGIC PWM ADAPTIVE ANTI CROSS CONDUCTION
CURRENT SHARING CORRECTION
HS2
LS2 LOGIC PWM ADAPTIVE ANTI CROSS CONDUCTION
CURRENT SHARING CORRECTION
HS3
SGND
3 PHASE OSCILLATOR
PWM1
PWM2
BOOT3
PWM3
OSC / EN / FAULT
PH1
PH2
PH3
PWM1 DIGITAL SOFT START
PWM2
PWM3
VCC OSC/EN/FAULT DAC_SEL
L6701 CONTROL LOGIC AND PROTECTIONS
OCP1 OCP2 OCP3 LOW SIDE MOSFET CURRENT READING AND OVER CURRENT
AVG
ISEN1 ISEN2 ISEN3
MULTIPLE DAC WITH DYNAMIC VID CONTROL
VID0 VID1 VID2 VID3 VID4 VID5 DAC_SEL
SSEND / PGOOD
IOS OVP UVP, PGOOD IINFO 1V SSEND / PGOOD 64k IDROOP
x3
DROOP CURRENT READING REMOTE BUFFER
64k
64k 64k
ERROR AMPLIFIER
VSEN
REF_OUT
REF_IN
COMP
FBR FBG
FB
CS-
CS+
13/44
6 VID Tables
L6701
6
Table 5.
VID Tables
Voltage IDentification (VID) for Intel VR10 DAC.
Output Voltage (1) 1.6000 1.5875 1.5750 1.5625 1.5500 1.5375 1.5250 1.5125 1.5000 1.4875 1.4750 1.4625 1.4500 1.4375 1.4250 1.4125 1.4000 1.3875 1.3750 1.3625 1.3500 1.3375 1.3250 1.3125 1.3000 1.2875 1.2750 1.2625 1.2500 1.2375 VID4 VID3 VID2 VID1 VID0 VID5 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Output Voltage (1) 1.2000 1.1875 1.1750 1.1625 1.1500 1.1375 1.1250 1.1175 1.1000 OFF OFF 1.0875 1.0750 1.0625 1.0500 1.0375 1.0250 1.0125 1.0000 0.9875 0.9750 0.9625 0.9500 0.9375 0.9250 0.9125 0.9000 0.8875 0.8750 0.8625
VID4 VID3 VID2 VID1 VID0 VID5 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
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L6701
Table 5. Voltage IDentification (VID) for Intel VR10 DAC. (continued)
Output Voltage (1) 1.2250 1.2125 VID4 VID3 VID2 VID1 VID0 VID5 0 0 1 1 0 0 0 1 1 0 1 0
6 VID Tables
VID4 VID3 VID2 VID1 VID0 VID5 1 1 1 1 0 0 0 1 1 0 1 0
Output Voltage (1) 0.8500 0.8375
1. Since the VIDx pins program the maximum output voltage, according to VR10.x specifications, the device automatically regulates to a voltage 19mV lower avoiding the use of any external components to lower the output voltage. This improves the system tolerance performance since the reference already offset is trimmed in production within 0.7%.
Table 6.
Voltage IDentification (VID) for Intel VR9 DAC (VID5 doesn't care)
Output Voltage(1) 1.850 1.825 1.800 1.775 1.750 1.725 1.700 1.675 1.650 1.625 1.600 1.575 1.550 1.525 1.500 1.475 VID4 VID3 VID2 VID1 VID0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output Voltage(1) 1.450 1.425 1.400 1.375 1.350 1.325 1.300 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 OFF
VID4 VID3 VID2 VID1 VID0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1. Since the VIDx pins program the maximum output voltage, the device automatically regulates to a voltage 19mV lower avoiding the use of any external components to lower the output voltage. This improves the system tolerance performance since the reference already offset is trimmed in production within 0.7%.
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6 VID Tables
L6701
Table 7.
Voltage IDentification (VID) for AMD Hammer DAC
Output Voltage 1.550 1.525 1.500 1.475 1.450 1.425 1.400 1.375 1.350 1.325 1.300 1.275 1.250 1.225 1.200 1.175 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 0.900 0.875 0.850 0.825 0.800 OFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 0.900 0.875 0.850 0.825 OFF VID5 VID4 VID3 VID2 VID1 VID0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output Voltage 1.575 1.550 1.525 1.500 1.475 1.450 1.425 1.400 1.375 1.350 1.325 1.300 1.275 1.250 1.225 1.200
VID5 VID4 VID3 VID2 VID1 VID0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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L6701
7 Configuring the Device: DAC Selection
7
Configuring the Device: DAC Selection
Multiple DACs need to be configured before the system start-up by programming the apposite pin DAC_SEL. The embedded DAC allows to regulate the output voltage with a tolerance of 0.7% recovering from offsets and manufacturing variations. In case of selecting VR9 and VR10 Mode, the device automatically introduces a -19mV offset to the regulated voltage (see Table 5 and Table 6) in order to avoid any external offset circuitry to worsen the guaranteed accuracy and, as a consequence, the calculated system TOB. In case of selecting the K8 DAC, VID5 gives the option to introduce +25mV offset to the regulation (See Table 7). Output voltage is programmed through the VID pins: they are inputs of an internal DAC that is realized by means of a series of resistors providing a partition of the internal voltage reference. The VID code drives a multiplexer that selects a voltage on a precise point of the divider. The DAC output is delivered to an amplifier obtaining the voltage reference available on REF_OUT. According to the selected DAC, the device also changes the protection thresholds as a consequence of different CPU specifications, see Table 8 for details. Table 8. L6701 Configuration
OPERATIVE MODE AMD K8 +25mV (Driven by VID5) Intel VR10 -19mV Intel VR9 -19mV OVP & PreOVP 1.9V Fixed 1.9V Fixed 2.1V Fixed UVP -400mV -400mV -400mV PGOOD -230mV SSEND -230mV
DAC_SEL OPEN 82k to GND GND
7.1
Single-Wire CPU Automatic Detection
L6701 has been designed to automatically detect the Intel CPU connected by monitoring the DAC_SEL pin status at the start-up so modifying the DAC table accordingly (see Table 8). In fact, by directly connecting the DAC_SEL pin with #BOOTSEL pin of the CPU, the controller automatically recognize the different technology steps of the CPU so modifying the DAC table accordingly. See CPU related documentation for further details about compatibility.
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8 Driver Section
L6701
8
Driver Section
The integrated high-current drivers allow using different types of power MOS (also multiple MOS to reduce the equivalent RDS(on)), maintaining fast switching transition. The drivers for the high-side MOSFETs use BOOTx pins for supply and PHASEx pins for return. The drivers for the low-side MOSFETs use the VCC pin for supply and PGND pin for return. The controller embodies a anti-shoot-through and adaptive dead-time control to minimize low side body diode conduction time maintaining good efficiency saving the use of Schottky diodes: when the high-side MOSFET turns off, the voltage on its source begins to fall; when the voltage reaches 2V, the low-side MOSFET gate drive is suddenly applied. When the low-side MOSFET turns off, the voltage at LGATEx pin is sensed. When it drops below 1V, the high-side MOSFET gate drive is suddenly applied. If the current flowing in the inductor is negative, the source of high-side MOSFET will never drop. To allow the low-side MOSFET to turn-on even in this case, a watchdog controller is enabled: if the source of the high-side MOSFET does not drop, the low side MOSFET is switched on so allowing the negative current of the inductor to recirculate. This mechanism allows the system to regulate even if the current is negative. Power conversion input is flexible: 5V, 12V bus or any bus that allows the conversion (See maximum duty cycle limitations) can be chosen freely.
8.1
Power Dissipation
L6701 embeds high current MOSFET drivers for both high side and low side MOSFETs: it is then important to consider the power that the device is going to dissipate in driving them in order to avoid overcoming the maximum junction operative temperature. In addition, since the device has an exposed pad to better dissipate the power, the thermal resistance between junction and ambient consequent to the layout is also important: thermal pad need to be soldered to the PCB ground plane through several VIAs in order to facilitate the heat dissipation. Two main terms contribute in the device power dissipation: bias power and drivers' power.
Device Power (PDC) depends on the static consumption of the device through the supply pins and it is simply quantifiable as follow (assuming to supply HS and LS drivers with the same VCC of the device): P DC = V CC ( I CC + 3 I CCDRx + 3 I BOO Tx )
Drivers' power is the power needed by the driver to continuously switch on and off the external MOSFETs; it is a function of the switching frequency and total gate charge of the selected MOSFETs. It can be quantified considering that the total power PSW dissipated to switch the MOSFETs (easy calculable) is dissipated by three main factors: external gate resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance. This last term is the important one to be determined to calculate the device power dissipation. The total power dissipated to switch the MOSFETs results: P SW = 3 F SW ( Q G HS V BO OT + Q GLS V CCDRx )
External gate resistors helps the device to dissipate the switching power since the same power PSW will be shared between the internal driver impedance and the external resistor resulting in a general cooling of the device.
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L6701
Figure 5. Dissipated Power
8 Driver Section
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9 Current Sharing Loop and Current Reading
L6701
9
9.1
Current Sharing Loop and Current Reading
Current Sharing Loop
L6701 embeds two separate Current Reading circuitries used to perform Current Sharing and OCP through ISENx pins and Voltage Positioning (Droop Function) through CS+ and CS- pins (See Section 10). Current sharing control loop and connections are reported in Figure 6: the current read through the ISENx pins is converted into a current IINFOx proportional to the current delivered by each phase and the information about the average current IAVG = IINFOx / 3 is internally built into the device. The error between the read current IINFOx and the reference IAVG is then converted into a voltage that with a proper gain is used to adjust the duty cycle whose dominant value is set by the voltage error amplifier in order to equalize the current carried by each phase.
9.2
Current Reading for Current Sharing
The current flowing trough each phase is read using the voltage drop across the low side MOSFETs RDS(on) or across a sense resistor in its series and it is internally converted into a current. The trans-conductance ratio is issued by the external resistor RISEN placed outside the chip between ISENx and the reading point (usually the LS MOSFET Drain). The current sense circuit tracks the current information for a time TTRACK centered in the middle of the LS conduction time and holds the tracked information during the rest of the period. The current that flows from the ISENx pin is the current information used by the device to perform current sharing and OCP and it is given by: R dsO N I ISENx = ----------------- I PHASEx = I INFO x R ISEN where RDS(on) is the ON resistance of the low side MOSFET and RISEN is the transconductance resistor connected between the ISENx pins and the LS Drain; IPHASEx is the current carried by the relative phase and IINFOx is the current information signal reproduced internally. RISENx is designed according to the Over Current Protection: see Section 13.6 for details. Figure 6. Current Sharing Loop and Current Reading Connections
IINFO1
PWM1 Out
IPHASEx
AVG
IAVG IINFO2
From EA PWM2 Out
LGATEx IISENx ISENx
RISEN
IINFO3
PWM3 Out
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L6701
10 Output Voltage Positioning
10
Output Voltage Positioning
Output voltage positioning is performed by selecting the reference DAC and by programming the Droop Function and Offset to the reference (See Figure 7). The current (IDROOP) sourced from the FB pin, directly proportional to the read current, causes the output voltage to vary according to the external RFB resistor so implementing the desired load-line resistance. The current (IOS) sourced from the REF_IN pin causes the reference voltage to be offset according to the resistance RFB connected. The output voltage is then driven by the following relationship: V O UT = VID + R O S I O S - R FB I DRO OP Both DROOP and OFFSET function can be disabled: see Section 10.1 and Section 10.3 for details. Figure 7. Voltage Positioning
64k
64k
VID
IDROOP
IOS
64k
64k
REF_OUT
REF_IN
FB RF RFB
COMP CF
VSEN
FBR
FBG
ROS COS
To Vcore
(Remote Sense)
10.1
Load-Line (Droop Function - Optional)
This method "recovers" part of the drop due to the output capacitor ESR in the load transient, introducing a dependence of the output voltage on the load current: a static error proportional to the output current causes the output voltage to vary according to the sensed current. Figure 8 shows the typical Current-Sense Circuit used to implement the Droop-Function in lowcost application (saves component count). The current flowing across the three inductors is read through the RPH - CPH filter across CS+ and CS- pins. RD programs a trans-conductance gain and generates a current ICS proportional to the average of the currents of the three phases. The current ICS is then mirrored and, multiplied by three, sourced by the FB pin (IDROOP). RFB gives the final gain to program the desired load-line slope. Considering the scheme reported on Figure 8, it is possible to observe that: I O UT 1 + s L DCR DCR I CS = ------------ --------------------------------------------------- -----------3 1 + s R PH C PH 3 R D Time constant matching between the inductor (L / DCR) and the current reading filter ( R PH C PH 3 ) is required to implement a real equivalent output impedance of the system so avoiding over and/or under shoot of the output voltage as a consequence of a load transient. It results:
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10 Output Voltage Positioning
L6701
R PH C PH I O UT DCR L ------------ = -------------------------- => I CS = ------------ -----------DCR 3 3 RD The device forces IDROOP = ICSx3, proportional to the read current, into the feedback resistor RFB implementing the load regulation dependence. The output characteristic vs. load current is then given by (Offset disabled): DCR V O UT = VID - R FB I DROOP = VID - R FB ------------ I OUT = VID - R LL I O UT RD Where RLL is the resulting load-line resistance implemented by the system. The whole power supply can be then represented by a "real" voltage generator with an equivalent output resistance RLL and a voltage value of VID. RFB resistor can be then designed according to the RLL specifications as follow: RD R FB = R L L -----------DCR where RD is typically designed to have ICS = 35A at the maximum output current (OCP).
Caution: Droop function is optional, in case it is not desired, the Current Sense circuit can be modified so
that the device always read a null current (See Figure 8). To do this, it is enough to connect CS+ directly to the output voltage leaving CS- unconnected. The reaction will keep CS+ and CS- at the same voltage, always reading a null current and also assuring the FB disconnection protection to be effective. Figure 8.
PHASE1 PHASE2
Droop Function Current Reading Network
L1 DCR1 PHASE1 L1 DCR1 L2 DCR2 PHASE2 VOUT L2 DCR2
PHASE3 RPH RPH RPH
L3
DCR3
PHASE3
L3
DCR3
VOUT
CPH RF RD CS+ CSFB
RFB CF
RFB CF
RF COMP CS+ CSFB
COMP
ICS x3
IDROOP
ICS x3
IDROOP
Droop Function Enabled
Droop Function Disabled
10.2
Fully-Differential Load-Line (Droop Function - Optional)
Fully-Differential current-reading for voltage-positioning allows the designer to save time in the application fine-tuning since the BOM so obtained becomes layout-independent. The patentpending topology offered by L6701 allow implementing fully-differential current-sense still using only two current-sense pins (CS+ and CS-). Figure 9 shows the typical Current-Sense Circuit used to implement the Fully-Differential Droop-Function. The current flowing across the three inductors is read through an RPH - CPH filter for each phase as well as an R D is required for each phase to program the trans-conductance-gain. As previously mentioned, a current ICS proportional to the average of the currents of the three phases is internally generated, mirrored
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L6701
10 Output Voltage Positioning
and, multiplied by three, sourced by the FB pin (IDROOP). RFB gives the final gain to program the desired load-line slope. As before, the voltage positioning equations results (See Figure 9): 1 + s L DCR DCR I CS = I O UT -------------------------------------------- -----------1+sR C R
PH PH D
As a consequence: L DCR ------------ = R PH C PH => I CS = I O UT -----------DCR RD The device forces IDROOP = ICSx3, proportional to the read current, into the feedback resistor RFB implementing the load regulation dependence. The output characteristic vs. load current is then given by (Offset disabled): DCR V O UT = VID - R FB I DROOP = VID - 3 R FB ------------ I O UT = VID - R L LDIFF I OUT RD Where RLLDIFF is the resulting differential load-line resistance implemented by the system. The whole power supply can be then represented by a "real" voltage generator with an equivalent output resistance RLLDIFF and a voltage value of VID. RFB resistor can be then designed according to the Load-Line (RLLDIFF) specifications as follow: R LL DIFF R D R FB = --------------------- ------------ . 3 DCR where RD is typically designed to have ICS = 35A at the maximum output current (OCP). Table 9 contains a quick-reference guide to design applications with typical and/or differential current sense. Figure 9. Fully Differential Load-Line Current-Reading (pat. pend.)
L1 DCR1
PHASE1
PHASE2
L2
DCR2
VOUT
PHASE3 RPH RPH RPH
L3
DCR3
Fully Differential Current Reading for Load-Line
CPH CPH CPH RD RD RD CSRF FB CF RFB
CS+
COMP
ICS x3
IDROOP
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10 Output Voltage Positioning
L6701
Table 9.
Comparison between different load-line implementations.
Fully-Differential LL Non-Fully-Differential LL N
Layout-insensitive BOM Time-Constant Matching
Y
L ------------ = R PH C PH DCR DCR R D = OCP -----------35 R LL R D R FB = --------- -----------3 DCR DCR R LL = 3 ------------ R FB RD
R PH C PH L ------------ = -------------------------DCR 3 OCP DCR R D = ------------ -----------3 35 RD R FB = R L L -----------DCR DCR R LL = ------------ R FB RD
R D Design (given OCP th.)
R FB Design (given RLL)
R LL (given RD and R FB)
10.3
Offset (Optional)
Positive offset can be added to the programmed reference by connecting a ROS resistor between the REF_OUT and REF_IN pins. Referring to Figure 7, a constant current (IOS=11.5A) is sourced from the REF_IN pin as soon as the device is enabled, so programming a fixed voltage drop across ROS: this voltage is directly added to the programmed reference giving the desired offset to the output voltage as follow: V O S = R OS I OS Offset current is suddenly sourced from REF_IN pin as soon as the device implements SoftStart: to avoid having steps during soft-start, the introduction of COS (in parallel to ROS) is required. The resulting time constant need to be negligible with respect to the soft-start time as well as long enough to smooth the initial step. Typical values are in the range of few hundreds of nF. Offset function can be easily disabled simply setting ROS = 0.
Caution: Offset automatically given by the DAC selection differs from the offset implemented through the
OFFSET pin: the built-in feature is trimmed in production and assures 0.7% accuracy over load and line variations.
10.4
Remote Voltage Sense
L6701 embeds a Remote Sense Buffer to sense remotely the regulated voltage without any additional external components. In this way, the output voltage programmed is regulated between the remote buffer inputs compensating motherboard or connector losses. The device senses the output voltage remotely through the pins FBR and FBG (FBR is for the regulated voltage sense while FBG is for the ground sense) and reports this voltage internally at VSEN pin with unity gain eliminating the errors. Keeping the FBR and FBG traces parallel and guarded by a power plane results in common mode coupling for any picked-up noise.
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L6701
10 Output Voltage Positioning
10.5
Maximum Duty Cycle limitation
To provide proper time for current-reading in order to equalize the current carried by each phase, the device implements a duty-cycle limitation. This limitation is not fixed but it is linearly variable with the current delivered to the load as follow: 0.80 T SW I ISENx = 0A T ON ( max ) = I ISENx = 35A 0.40 T SW Duty Cycle limitation is variable with the delivered current to provide fast load transient response at light load as well as assuring robust over-current protection. Figure 10 shows the maximum output voltage that the device is able to regulate considering the TON limitation imposed by the previous relationship. If the desired output characteristic crosses the limited-TON maximum output voltage, the output resulting voltage will start to drop after the cross-point. In this case, the output voltage starts to decrease following the resulting characteristic (dotted in Figure 10) until UVP is detected or anyway until IISENx = 35A. Figure 10. Maximum Duty Cycle limitation

Maximum Output Voltage VOUT 0.80 VIN VOUT 0.80 VIN
Limited TON
0.40 VIN Limted-TON Output Char.
0.40 VIN Limted-TON Output Char. Desired output Char. Resulting Output Char. UVP Threshold IOUT IOCP = 3 x IOCPx (IISENx = 35A) IOCP = 3 x IOCPx (IISENx = 35A) IOUT
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11 Dynamic VID Transitions
L6701
11
Dynamic VID Transitions
L6701 is able to manage Dynamic VID Code changes in all its operative modes (VR10, K8 and also VR9) so allowing Output Voltage modification during normal device operation. PGOOD (when applicable), OVP and UVP signals are masked during every VID transition and they are re-activated after the transition finishes with a 32 clock cycles delay to prevent from false triggering. When changing dynamically the regulated voltage (D-VID), the system needs to charge or discharge the output capacitor accordingly. This means that an extra-current
ID - VID = C OUT dV OU T dT VI D
needs to be delivered, especially when increasing the output regulated voltage and it must be considered when setting the over current threshold. In the previous relationship, dVOUT is the selected DAC LSB (12.5mV for VR10 DAC or 25mV for both VR9 and K8 DACs) and TVID is the time interval between each LSB transition (typically externally driven). Overcoming the OC threshold during the dynamic VID causes the device to enter the constant current limitation slowing down the output voltage dV/dt also causing the failure in the D-VID test. Figure 11. Dynamic VID Transitions
Ref Moved (2) Ref Moved (3) Ref Moved (4) VID Sampled VID Stable Ref Moved (1) VID Sampled VID Stable Ref Moved (1) VID Sampled VID Stable Ref Moved (1) VID Sampled VID Stable Ref Moved (1) VID Sampled VID Stable Ref Moved (1) VID Sampled VID Sampled VID Sampled VID Sampled VID Sampled VID Sampled VID Sampled VID Sampled VID Sampled VID Sampled VID Sampled VID Sampled
VID Clock
VID [0,5]
t
Int. Reference TDVID
t
Tsw Vout TVID
t
x 4 Step VID Transition Vout Slope Controlled by internal DVID-Clock Oscillator
4 x 1 Step VID Transition Vout Slope Controlled by external driving circuit (TVID)
t
L6701 checks for VID code modifications (See Figure 11) on the rising edge of an internal additional DVID-clock and waits for a confirmation on the following falling edge. Once the new code is stable, on the next rising edge, the reference starts stepping up or down in LSB increments every VID-clock cycle until the new VID code is reached. During the transition, VID code changes are ignored; the device re-starts monitoring VID after the transition has finished on the next rising edge available. VID-clock frequency (FDVID) depends on the operative mode selected: for VR10 Mode it is equal to three times the system switching frequency programmed for each phase (FDVID = 3 x FSW) to assure compatibility with the specifications while, for VR9 and K8, this frequency is lowered to FDVID = FSW.
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L6701
11 Dynamic VID Transitions
Caution: If the new VID code is more than 1 LSB different from the previous, the device will execute the
transition stepping the reference with the DVID-clock frequency FDVID until the new code has reached: for this reason it is recommended to carefully control the VID change rate in order to carefully control the slope of the output voltage variation especially in VR10 mode.
Warning: DVID sample and hold clock depends on the switching frequency FSW. To correctly perform
DVID transition so following the VID change rate, it is required to have at least 2 complete cycles of the FDVID clock between every VID transition. If the VID update-rate is, for example, 5sec., the minimum operating frequency results to be FSW > 133kHz in VR10 mode.
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12 Soft Start
L6701
12
Soft Start
L6701 implements a soft-start to smoothly charge the output filter avoiding high in-rush currents to be required to the input power supply. The device increases the reference from zero up to the programmed value in 2048 clock periods and the output voltage increases accordingly with closed loop regulation. At the end of the digital Soft-Start, SSEND/PGOOD signal is set free. Protections are active during this phase; Under Voltage is enabled when the reference voltage reaches 0.6V while Over Voltage is always enabled with a threshold dependent on the selected Operative Mode. DAC table information is frozen just before initializing the Soft-Start. The device implements Soft-Start only when all the power supplies are above their own turn-on thresholds and the EN pin is set free.
12.1
Low-Side-Less Startup (LSLess)
In order to avoid any kind of negative undershoot and dangerous return from the load during start-up, L6701 performs a special sequence in enabling LS driver to switch: during the softstart phase, the LS driver results disabled (LS = OFF) until the HS starts to switch. This avoid the dangerous negative spike on the output voltage that can happen if starting over a prebiased output (See Figure 12). This particular feature of the device masks the LS turn-on only from the control loop point of view: protections by-pass this turning ON the LS MOSFET in case of need. Figure 12. LSLess Startup (left) vs. Non-LSLess Startup (right)
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L6701
13 Output voltage Monitor and Protections
13
Output voltage Monitor and Protections
L6701 monitors through pin VSEN the regulated voltage in order to manage the OVP, UVP and PGOOD (when applicable) conditions. Protections are active also during soft-start (See Section 12 for details) while are masked during D-VID transitions with an additional 32 clock cycle delay after the transition has finished to avoid false triggering. In addition, preliminary over-voltage protection is also provided to protect the load from highside MOSFET failures before the system turn-ON.
13.1
Under Voltage
If the output voltage monitored by VSEN drops more than -400mV below the programmed reference for more than one clock period, the device turns off all MOSFETs driving high the FAULT pin and latches the condition: to recover it is required to cycle Vcc or the EN pin. This is independent by the selected operative mode.
13.2
Preliminary Over Voltage
To provide a protection while VCC is below the UVLOVCC threshold is fundamental to avoid damage to the load in case of failed HS MOSFETs. In fact, since the device is supplied from the 12V bus, it is basically "blind" for any voltage below the turn-on threshold (UVLOVCC). In order to give full protection to the load, a preliminary-OVP protection is provided while VCC is within UVLOVCC and UVLOOVP. According to the DAC_SEL pin status, this protection turns-on the low side MOSFETs as long as the FBR pin voltage is greater than 1.9V for VR10 and 2.1V for VR9 and K8 with a 300mV hysteresis (See Table 10). When set, the protection drives the LS MOSFET with a gate-tosource voltage depending on the voltage applied to VCC. This protection depends also on the EN pin status as detailed in Figure 13. Preliminary OVP is always active before UVLOVCC for all operative modes with intervention thresholds dependent on the DAC_SEL pin status. A simple way to provide protection to the output in all conditions when the system is OFF (then avoiding the unprotected red region in Figure 13-Left) consists in supplying the controller through the 5VSB bus with an OR-ing diode solution as shown in Figure 13-Right: 5VSB is always present before +12V and, in case of HS short, the LS MOSFET is driven with 5V assuring a reliable protection of the load. When using the OR-ing diode solution, OR-ing diodes need to be sized according to the device current consumption: the two diodes will then results to be different since the diode connected to the 12V bus needs to carry the current for normal operations (IRMS) and the diode connected to the 5VSB (IRMS-PREOVP) need to carry only the current in case of Pre-OVP protection is active. Device current consumption (IRMS) in normal operations depends on the external MOSFET configuration as follow: I RMS = 3 FSW ( Q G HS + Q GLS ) + ( I CC + 3 I CCDRx + 3 I BOO Tx ) Device current consumption when Pre-OVP is active depends on the output filter configuration since LS MOSFETs switching frequency depends on the leakage that is charging the output filter. Test on the bench is required but, for an over-sized solution, the same diode identified for the +12V bus can be used.
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13 Output voltage Monitor and Protections
L6701
Figure 13. Output Voltage Protections and typical principle connections
Vcc UVLOVCC
(EN = 0) Preliminary OVP FBR/DACSEL Monitor
(EN = Free) OVP Protection VSEN Monitored
+5V
SB
Preliminary OVP Enabled FBR Monitored UVLOOVP No Protection Provided
+12V
VCC
13.3
Over Voltage
Once VCC crosses the turn-ON threshold and the device is enabled (EN = Free), L6701 provides an Over Voltage Protection according to the DAC_SEL status: when the voltage sensed by VSEN overcomes the OVP threshold, the controller permanently switches on all the low-side MOSFETs and switches off all the high-side MOSFETs in order to protect the load. The FAULT pin is driven high (5V) and power supply or EN pin cycling is required to restart operations. The OVP (and Pre-OVP) Threshold varies according to the operative mode selected as reported in Table 10. Table 10. OVP and Preliminary OVP Thresholds
Operative Mode VR9 VR10 K8 Pre-OVP 2.1 1.9 1.9 OVP 2.1 1.9 1.9
DAC_SEL 0 82k to SGND Open
13.4
Feedback Disconnection
L6701 allows to monitor the output voltage in two different points:

Remotely, through the remote buffer, across VSEN Locally across the CS- pin (negligibly offset by R D I C S ).
By comparing the voltage present at these two different locations, L6701 is able to understand if the output voltage feedback is connected. When CS- is more than 1V higher than VSEN, (See Figure 14) the device stops switching with the low side MOSFETs permanently ON and drives high the FAULT pin. The condition is latched until VCC or EN cycled.
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L6701
Figure 14. Feedback Disconnection
PHASE1 L1 DCR1 L2 DCR2
13 Output voltage Monitor and Protections
PHASE2
PHASE3
L3
DCR3
VOUT
RD RD RD CD RF RG CS_DROOP+ CS_DROOPFB COMP VSEN FBR FBG RFB CF
IINFO x3
IDROOP
VID 1V
FB_DISCONNECTED
13.5
PGOOD (Only for VR9 and K8 Modes)
It is an open-drain signal set free after the soft-start sequence has finished. It is pulled low when the output voltage drops below -230mV of the programmed voltage.
13.6
Over Current Protection
Output current in each phase is monitored by L6701 through RISEN and so, programming the value of these resistors, it is possible to set the OCP to the desired value. The Over Current threshold has to be programmed to a safe value, in order to be sure that the device doesn't enter OCP during normal operation of the device. This value must take into consideration also the extra current needed during the Dynamic VID Transition ID-VID and, since the device reads across MOSFETs RDS(on), the process spread and temperature variations of these sensing elements. Moreover, since also the internal threshold spreads, the Rg design has to consider the minimum value IOCTH(min) of the threshold as follow: I OCPx ( m ax ) R dsO N ( max ) Rg = ----------------------------------------------------------------I O CTH ( m in ) where IOCPx is the current measured by the current reading circuitry when the device enters Quasi-Constant-Current. Since the device reads the current across Low Side MOSFETs, it limits the bottom of the inductor current entering in constant current until setting UVP as below explained. IOCPx must be calculated starting from the corresponding output current value IOUT(OCP) as follow (ID-VID must also be considered when D-VID are supported) since the device holds the valley current information: I OUT ( O CP ) I PP I D - VID I O CPx = --------------------------- - ----------- + -----------------3 2 3 where IOUT(OCP) is still the output current value at which the device enters Quasi-ConstantCurrent, IPP is the inductor current ripple in each phase and ID-VID is the additional current required by D-VID (when applicable). In particular, since the device limits the valley of the
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13 Output voltage Monitor and Protections
L6701
inductor current, the ripple entity, when not negligible, impacts on the real OC threshold value and must be considered. The device detects an Over Current condition for each phase when the current information IISENx overcomes the fixed threshold of IOCTH. When this happens, the device keeps the relative LS MOSFET on, also skipping clock cycles, until the threshold is crossed back and IISENx results being lower than the IOCTH threshold (this implies that the device limits the bottom of each inductor current ripple). After exiting the OC condition, the LS MOSFET is turned off and the HS is turned on with a duty cycle driven by the PWM comparator. The device enters in Quasi-Constant-Current operation: the low-side MOSFETs stays ON until the current read becomes lower than IOCPx (IINFOx < I OCTH) skipping clock cycles. The high side MOSFET can be then turned ON with a TON imposed by the control loop after the LS turnoff and the device works in the usual way until another OCP event is detected. This means that the average current delivered can slightly increase in Quasi-Constant-Current operation since the current ripple increases. In fact, the ON time increases due to the OFF time rise because of the current has to reach the IOCPx bottom. The worst-case condition is when the ON time reaches its maximum value (see Section 10.5). When this happens, the device works in Real Constant Current and the output voltage decrease as the load increase. Crossing the UVP threshold causes the device to latch driving high the OSC pin. It can be observed that the peak current (IPEAK) is greater than IOCPx but it can be determined as follow: V IN - V OUT ( m in ) V IN - V O UT ( min ) I PEAK = I OCPx + ------------------------------------------ T ON ( m ax ) = I O CPx + ------------------------------------------ 0.40 T SW L L Where VoutMIN is the UVP threshold, (inductor saturation must be considered). When that threshold is crossed, all MOSFETs are turned off, the FAULT pin is driven high and the device stops working. Cycle the power supply or the EN pin to restart operation. The maximum average current during the Constant-Current behavior results (see Figure 15): I PEAK - I O CPx I MAX, tot = 3 IMAX = 3 IOCPx + -----------------------------------2 in this particular situation, the switching frequency for each phase results reduced. The ON time is the maximum allowed TON(max) while the OFF time depends on the application: I PEAK - I OCPx 1 T OFF = L -----------------------------------f = --------------------------------------------T O N ( max ) + T OFF V OUT Figure 15. Constant Current Operation
Constant Current (Exploded) IPEAK IMAX Droop Effect
Quasi-Const. Current
VOUT 0.40 VIN
IOCPx TON(max) TON(max) Limted-TON Char. Resulting Out. Char. UVP Threshold
LS ON Skipping Clock Cycles
TSW
TSW
IOCP = N x IOCPx (IDROOP = N x 35A)
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IOUT IMAX,tot
L6701
13 Output voltage Monitor and Protections
The trans-conductance resistor RISENx can be designed considering that the device limits the bottom of the inductor current ripple and also considering the additional current delivered during the quasi-constant-current behavior as previously described in the worst case conditions. Moreover, when designing D-VID compatible systems, the additional current due to the output filter charge during dynamic VID transitions must be considered. I O CPx ( max ) R ds ON ( m ax ) I OUT ( O CP ) I PP I D - VID R ISENx = ----------------------------------------------------------------- where I O CPx = --------------------------- - ----------- + -----------------3 2 3 I OCTH ( min )
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14 Oscillator
L6701
14
Oscillator
The internal oscillator generates the triangular waveform for the PWM charging and discharging with a constant current an internal capacitor. The switching frequency for each channel, FSW, is internally fixed at 100kHz so that the resulting switching frequency at the load side results in being tripled (300kHz). The current delivered to the oscillator is typically 25A (corresponding to the free-running frequency FSW=100kHz) and it may be varied using an external resistor (ROSC) connected between the OSC pin and SGND. Since the OSC pin is fixed at 1.24V, the frequency is increased proportionally to the current sunk from the pin considering the internal gain of 4KHz/ A. In particular connecting ROSC to SGND the frequency is increased according to the following relationship: 1.240V kHz 4.96 10 ROSC vs. SGND F SW = 100kHz + ---------------------------- 4 ---------- = 100kHz + ---------------------------R R ( k ) A ( k )
OSC OSC 6
Caution: Maximum programmable switching frequency per phase must be limited to 500kHz to avoid
current reading errors causing, as a consequence, current sharing errors. Anyway, device power dissipation must be checked prior to design high switching frequency systems. Figure 16. ROSC vs. Switching Frequency
250
Rosc [kOhms] to SGND
200
150
100
50
0 100
150
200
250
300
350
400
450
500
550
Fsw [kHz] Programmed
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L6701
15 System Control Loop Compensation
15
System Control Loop Compensation
The control loop is composed by the Current Sharing control loop (See Figure 17) and the Average Current Mode control loop. Each loop gives, with a proper gain, the correction to the PWM in order to minimize the error in its regulation: the Current Sharing control loop equalize the currents in the inductors while the Average Current Mode control loop fixes the output voltage equal to the reference programmed by VID. Figure 17 shows the block diagram of the system control loop. The system Control Loop is reported in Figure 18. The current information IDROOP sourced by the DROOP pin flows into RFB implementing the dependence of the output voltage from the read current.
Figure 17. Main Control Loop
L3 PWM3 1/5 L2 PWM2 1/5 L1 PWM1 1/5 ERROR AMPLIFIER Reference 4/5 IDROOP COMP FB COUT ROUT
CURRENT SHARING DUTY CYCLE CORRECTION
IINFO1 IINFO2 IINFO3
ZF(s)
ZF(s)
The system can be modeled with an equivalent single phase converter which only difference is the equivalent inductor L/3 (where each phase has an L inductor).The Control Loop gain results (obtained opening the loop after the COMP pin): PWM Z F ( s ) ( R DROOP + Z P ( s ) ) G LOO P ( s ) = - ------------------------------------------------------------------------------------------------------------------ZF ( s ) 1 [ Z P ( s ) + Z L ( s ) ] -------------- + 1 + ----------- R FB A(s ) A(s ) Where:
DCR R D ROOP = ------------- R FB is the equivalent output resistance determined by the droop function RD
DCR ( R DROO P = 3 ------------ R FB R
D
for fully differential current sense);
ZP(s) is the impedance resulting by the parallel of the output capacitor (and its ESR) and the applied load RO; ZF(s) is the compensation network impedance; ZL(s) is the parallel of the three inductor impedance; A(s) is the error amplifier gain;

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15 System Control Loop Compensation
L6701
V IN 4 PWM = -- ------------------ is the PWM transfer function where VOSC is the oscillator ramp 5 V OSC
amplitude and has a typical value of 3V. Removing the dependence from the Error Amplifier gain, so assuming this gain high enough, and with further simplifications, the control loop gain results:
G LOOP V IN 4 ( s ) = - -- --------------------- 5 V OSC Z (s ) R + R 1 + s C (R //R + ESR ) F O DR OOP O DROOP O --------------- ------------------------------------------- -----------------------------------------------------------------------------------------------------------------------------------------R R R 2 L L FB L L R + ------s C --- + s ----------------- + C ESR + C ------- + 1 O3 O3 O3 3 RO O
The system Control Loop gain (See Figure 18) is designed in order to obtain a high DC gain to minimize static error and to cross the 0dB axes with a constant -20dB/dec slope with the desired crossover frequency T. Neglecting the effect of ZF(s), the transfer function has one zero and two poles; both the poles are fixed once the output filter is designed (LC filter resonance LC) and the zero (ESR) is fixed by ESR and the Droop resistance. Figure 18. Equivalent Control Loop Block Diagram (left) and Bode Diagram (right).
PWM d VOUT L / N ESR CO REMOTE BUFFER 64k IDROOP Reference VOUT 64k FBG FBR K RF[dB] ZF(s) RO GLOOP(s) VOUT dB
64k DROOP FB RF ZF(s) ZFB(s) RFB COMP CF
VSEN
LC = F ESR
T
To obtain the desired shape an RF - CF series network is considered for the ZF(s) implementation. A zero at F = 1/RFCF is then introduced together with an integrator. This integrator minimizes the static error while placing the zero F in correspondence with the L-C resonance assures a simple -20dB/dec shape of the gain. In fact, considering the usual value for the output filter, the LC resonance results to be at frequency lower than the above reported zero. Compensation network can be simply designed placing F=LC and imposing the cross-over frequency T as desired obtaining (always considering that T might be not higher than 1/10th of the switching frequency FSW): L C O -R FB V O SC 5 3 L R F = ---------------------------------- -- T ------------------------------------------------------ C F = ------------------4 RF 3 ( R DROOP + ESR ) V IN
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L6701
15 System Control Loop Compensation
15.1
Compensation Network Guidelines
The Compensation Network design assures to having system response according to the crossover frequency selected and to the output filter considered: it is anyway possible to further finetune the compensation network modifying the bandwidth in order to get the best response of the system as follow (See Figure 19):

Increase RF to increase the system bandwidth accordingly; Decrease RF to decrease the system bandwidth accordingly; Increase CF to move F to low frequencies increasing as a consequence the system phase margin.
Having the fastest compensation network gives not the confidence to satisfy the requirements of the load: the inductor still limits the maximum dI/dt that the system can afford. In fact, when a load transient is applied, the best that the controller can do is to "saturate" the duty cycle to its maximum (dMAX) or minimum (0) value. The output voltage dV/dt is then limited by the inductor charge / discharge time and by the output capacitance. In particular, the most limiting transition corresponds to the load removal since the inductor results being discharged only by VOUT (while it is charged by dMAXVIN-VOUT during a load appliance). Referring to Figure 19-left, further tuning the Compensation network cannot give any improvements unless the output filter changes: only modifying the main inductors or the output capacitance improves the system response. Figure 19. Best Load Transient achievable (d=0) and R F-CF impact on Bandwidth.
dB CF GLOOP(s) K RF[dB] RF ZF(s)
LC = F ESR
T
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16 Layout Guidelines
L6701
16
Layout Guidelines
Since the device manages control functions and high-current drivers, layout is one of the most important things to consider when designing such high current applications. A good layout solution can generate a benefit in lowering power-dissipation on the power paths, reducing radiation and a proper connection between signal and power ground can optimize the performance of the control loops. Two kind of critical components and connections have to be considered when layouting a VRM based on L6701: power components and connections and small signal components connections.
16.1
Power Components and Connections
These are the components and connections where switching and high continuous current flows from the input to the load. The first priority when placing components has to be reserved to this power section, minimizing the length of each connection and loop as much as possible. To minimize noise and voltage spikes (EMI and losses) these interconnections must be a part of a power plane and anyway realized by wide and thick copper traces: loop must be anyway minimized. The critical components, i.e. the power transistors, must be close one to the other. The use of multi-layer printed circuit board is recommended. Figure 20 shows the details of the power connections involved and the current loops. The input capacitance (CIN), or at least a portion of the total capacitance needed, has to be placed close to the power section in order to eliminate the stray inductance generated by the copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be connected near the HS drain. Use proper VIAs number when power traces have to move between different planes on the PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the same high-current trace on more than one PCB layer will reduce the parasitic resistance associated to that connection. Connect output bulk capacitor as near as possible to the load, minimizing parasitic inductance and resistance associated to the copper trace also adding extra decoupling capacitors along the way to the load when this results in being far from the bulk capacitor bank. Gate traces must be sized according to the driver RMS current delivered to the power MOSFET. The device robustness allows managing applications with the power section far from the controller without losing performances. Anyway, when possible, it is suggested to minimize the distance between controller and power section.
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L6701
16 Layout Guidelines
16.2
Small Signal Components and Connections
These are small signal components and connections to critical nodes of the application as well as bypass capacitors for the device supply (See Figure 20). Locate the bypass capacitor (VCC and Bootstrap capacitor) close to the device and refer sensible components such as frequency set-up resistor ROSC to SGND. Star grounding is suggested: connect SGND to PGND plane in a single point to avoid that drops due to the high current delivered causes errors in the device behavior. VSEN pin filtered vs. SGND helps in reducing noise injection into device: take care in routing driving net for this pin in order to minimize coupled noise. Remote Buffer Connection must be routed as parallel nets from the FBG/FBR pins to the load in order to avoid the pick-up of any common mode noise. Connecting these pins in points far from the load will cause a non-optimum load regulation, increasing output tolerance. Locate current reading components close to the device. It's also important to minimize any offset in the measurement and, to get a better precision, to connect the traces as close as possible to the sensing elements.
Caution: Boot Capacitor Extra Charge. Systems that do not use Schottky diodes might show big
negative spikes on the phase pin. This spike can be limited as well as the positive spike but has an additional consequence: it causes the bootstrap capacitor to be over-charged. This extracharge can cause, in the worst case condition of maximum input voltage and during particular transients, that boot-to-phase voltage overcomes the abs. max. ratings also causing device failures. It is then suggested in this cases to limit this extra-charge by: - - adding a small resistor in series to the boot diode (one resistor can be enough for all the three diodes if placed upstream the boot diode anode, see Figure 20) using non-capacitive boot diodes (such as standard diodes).
Figure 20. Power connections and related connections layout (same for all phases).
To limit CBOOT Extra-Charge VIN BOOTx VIN
CBOOT
UGATEx PHASEx
CIN L
CIN L
PHASEx VCC
LGATEx PGNDx
LOAD SGND +Vcc
LOAD
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16 Layout Guidelines
L6701
16.3
Embedding L6701-based VRs
When embedding the VR into the application, additional care must be taken since the whole VR is a switching DC/DC regulator and the most common systems in which it has to work are digital systems such as MB or similar. In fact, latest MB has become faster and powerful: high speed data bus are more and more common and switching-induced noise produced by the VR' MOSFETs can affect data integrity if not following additional layout guidelines. Few easy points must be considered mainly when routing traces and planes in which high switching currents flow (high switching currents cause voltage spikes across the stray inductance of the trace causing noise that can affect the near traces): Keep safe guarding distance between high current switching VRD traces and data buses, especially if high-speed data bus to minimize noise coupling. Keep safe guard distance or filter properly when routing bias traces for I/O sub-systems that must walk near the VRD. Possible causes of noise can be located in the PHASE connections, MOSFET gate drive and Input voltage path (from input bulk capacitors and HS drain). Also PGND connections must be considered if not insisting on a power ground plane. These connections must be carefully kept far away from noise-sensitive data bus. Since the generated noise is mainly due to the switching activity of the VR, noise emissions depend on how fast the current switches. To reduce noise emission levels, it is also possible, in addition to the previous guidelines, to reduce the current slope by properly tuning the HS gate resistor and the PHASE snubber network.
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L6701
17 Package Mechanical Data
17
Package Mechanical Data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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17 Package Mechanical Data
L6701
PowerSSO-36 Mechanical Data
Dim. A A2 a1 b c D (1) E(2) e e3 F G G1 H h L M N O Q S T U X Y mm Min. 2.15 2.15 0 0.18 0.23 10.10 7.4 0.50 8.50 2.3 0.10 0.06 10.50 0.40 0.85 4.3 10 (max) 1.2 0.8 2.9 3.65 1.0 4.10 6.50 4.70 7.10 0.161 0.256 0.047 0.031 0.114 0.144 0.039 0.185 0.279 Typ. Max. 2.47 2.40 0.075 0.36 0.32 10.50 7.6 Min. 0.084 0.084 0 0.007 0.009 0.398 0.291 0.020 0.035 0.090 0.004 0.002 0.413 0.016 0.033 0.169 inch Typ. Max. 0.097 0.094 0.003 0.014 0.012 0.413 0.299
10.10 0.55
0.398 0.022
1. "D and E" do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.006") 2. No intrusion allowed inwards the leads. 3. Flash or bleeds on exposed die pad shall not exceed 0.4 mm per side
Figure 21. Package Dimensions
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L6701
18 Revision history
18
Revision history
Date 13-Dec-2005 Revision 1 First draft Description of Changes
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18 Revision history
L6701
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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